Journal Sciences News
Zoologischer Anzeiger, A Journal of Comparative Zoology
July 2018
Low voltage operation of GaN vertical nanowire MOSFET
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Dong-Hyeok Son, Young-Woo Jo, Jae Hwa Seo, Chul-Ho Won, Ki-Sik Im, Yong Soo Lee, Hwan Soo Jang, Dae-Hyun Kim, In Man Kang, Jung-Hee Lee GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300
June 2018
Numerical modeling of reverse recovery characteristic in silicon pin diodes
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Yusuke Yamashita, Hiroshi Tadano A new numerical reverse recovery model of silicon pin diode is proposed by the approximation of the reverse recovery waveform as a simple shape. This is the first model to calculate the reverse recovery characteristics using numerical equations without adjusted by fitting equations and fitting parameters. In order to verify the validity and the accuracy of the numerical model, the calculation result from the model is verified through the device simulation result.
June 2018
Editorial Board
Publication date: June 2018
Source:Solid-State Electronics, Volume 144

June 2018
Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Junjie Guo, Dingdong Xie, Bingchu Yang, Jie Jiang Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5
June 2018
Hybrid solar cells composed of perovskite and polymer photovoltaic structures
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Apatsanan Phaometvarithorn, Surawut Chuangchote, Pisist Kumnorkaew, Jatuphorn Wootthikanokkhan Organic/inorganic lead halide perovskite solar cells have recently attracted much attention in photovoltaic research, due to the devices show promising ways to achieve high efficiencies. The perovskite devices with high efficiencies, however, are typically fabricated in tandem solar cell which is complicated. In this research work, we introduce a solar cell device with the combination of CH3NH3PbI3
June 2018
A new high-
June 2018
Contacting graphene in a 200
June 2018
Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Lei Qiang, Xiaoci Liang, Guangshuo Cai, Yanli Pei, Ruohe Yao, Gang Wang Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: E C
June 2018
Performance enhancement of pentacene-based organic thin-film transistors using 6,13-pentacenequinone as a carrier injection interlayer
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Ching-Lin Fan, Wei-Chun Lin, Hao-Wei Chen This work demonstrates pentacene-based organic thin-film transistors (OTFTs) fabricated by inserting a 6,13-pentacenequinone (PQ) carrier injection layer between the source/drain (S/D) metal Au electrodes and pentacene channel layer. Compared to devices without a PQ layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off current ratio were significantly improved for the device with a 5-nm-thick PQ interlayer. These improvements are attributed to significant reduction of hole barrier height at the Au/pentacene channel interfaces. Therefore, it is believed that using PQ as the carrier injection layer is a good candidate to improve the pentacene-based OTFTs electrical performance.
June 2018
A new approach to the extraction of single exponential diode model parameters
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Adelmo Ortiz-Conde, Francisco J. Garc
June 2018
The photovoltaic impact of atomic layer deposited TiO2 interfacial layer on Si-based photodiodes
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Abdulkerim Karabulut,
June 2018
Circular electrodes to reduce the current variation of OTFTs with the drop-casted semiconducting layer
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): H.M. Dipu Kabir, Zubair Ahmed, Remashan Kariyadan, Lining Zhang, Mansun Chan Circular organic thin film transistor (OTFT) structures are proposed to reduce the impact of variable grain alignment on the drive current of the polycrystalline organic thin film transistor (OTFT). As the circular structure is planar symmetric, the orientation of the grain cannot affect the drive current of the circular OTFT. Thus, circular electrodes expected to provide a lower variation. Top-gate, bottom-contact circular and conventional OTFTs with drop-casted polycrystalline 6,13-Bis(triisopropyl-silylethynyl) (TIPS)-Pentacene organic semiconducting layer (OSC) are fabricated to verify the theoretical variation reduction. The relative standard deviation (RSD), defined as the ratio of standard deviation and the average of drive current is used as the degree of variations in different structures. According to our fabrication result, circular transistors have a significantly lower variation (20% RSD), compared to the variation of conventional OTFTs (61% RSD).

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June 2018
Modeling of an 8–12
June 2018
Analysis of reverse gate leakage mechanism of AlGaN/GaN HEMTs with N2 plasma surface treatment
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Hui Liu, Zongjing Zhang, Weijun Luo The mechanism of reverse gate leakage current of AlGaN/GaN HEMTs with two different surface treatment methods are studied by using C-V, temperature dependent I–V and theoretical analysis. At the lower reverse bias region (VR
June 2018
A charge-based model of Junction Barrier Schottky rectifiers
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Alvaro D. Latorre-Rey, Mihir Mudholkar, Mohammed T. Quddus, Ali Salih A new charge-based model of the electric field distribution for Junction Barrier Schottky (JBS) diodes is presented, based on the description of the charge-sharing effect between the vertical Schottky junction and the lateral pn-junctions that constitute the active cell of the device. In our model, the inherently 2-D problem is transformed into a simple but accurate 1-D problem which has a closed analytical solution that captures the reshaping and reduction of the electric field profile responsible for the improved electrical performance of these devices, while preserving physically meaningful expressions that depend on relevant device parameters. The validation of the model is performed by comparing calculated electric field profiles with drift-diffusion simulations of a JBS device showing good agreement. Even though other fully 2-D models already available provide higher accuracy, they lack physical insight making the proposed model an useful tool for device design.
June 2018
Performance analysis and simulation of vertical gallium nitride nanowire transistors
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Bernd Witzigmann, Feng Yu, Kristian Frank, Klaas Strempel, Muhammad Fahlesa Fatahilah, Hans Werner Schumacher, Hutomo Suryo Wasisto, Friedhard R
June 2018
New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): C. Diaz Llorente, C. Le Royer, P. Batude, C. Fenouillet-Beranger, S. Martinie, C.-M.V. Lu, F. Allain, J.-P. Colinge, S. Cristoloveanu, G. Ghibaudo, M. Vinet This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.
June 2018
Graphene/black phosphorus heterostructured photodetector
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Jiao Xu, Young Jae Song, Jin-Hong Park, Sungjoo Lee Graphene photodetectors exhibit a low photoresponsivity due to their weak light absorbance. In this study, we fabricated a graphene/black phosphorus (BP) heterostructure, in which the multilayer BP flake with a
June 2018
Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Jonas Heidler, Sheng Yang, Xinliang Feng, Klaus M
June 2018
Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Yong-Jung Cho, Woo-Sic Kim, Yeol-Hyeong Lee, Jeong Ki Park, Geon Tae Kim, Ohyun Kim We investigated the mechanism of formation of the hump that occurs in the current-voltage I-V characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) that are exposed to long-term drain bias stress under illumination. Transfer characteristics showed two-stage degradation under the stress. At the beginning of the stress, the I-V characteristics shifted in the negative direction with a degradation of subthreshold slope, but the hump phenomenon developed over time in the I-V characteristics. The development of the hump was related to creation of defects, especially ionized oxygen vacancies which act as shallow donor-like states near the conduction-band minimum in a-IGZO. To further investigate the hump phenomenon we measured a capacitance-voltage C-V curve and performed two-dimensional device simulation. Stretched-out C-V for the gate-to-drain capacitance and simulated electric field distribution which exhibited large electric field near the drain side of TFT indicated that V O 2+ were generated near the drain side of TFT, but the hump was not induced when V O 2+ only existed near the drain side. Therefore, the degradation behavior under DBITS occurred because V O 2+ were created near the drain side, then were migrated to the source side of the TFT.
Available online 11 April 2018
Evidence of low injection efficiency for implanted p-emitters in bipolar 4H-SiC high-voltage diodes
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Christian D. Matthus, Andreas Huerner, Tobias Erlbacher, Anton J. Bauer, Lothar Frey In this study, the influence of the emitter efficiency on the forward current–voltage characteristics, especially the conductivity modulation of bipolar SiC-diodes was analyzed. It was determined that the emitter efficiency of p-emitters formed by ion implantation is significantly lower compared to p-emitters formed by epitaxy. In contrast to comparable studies, experimental approach was arranged that the influence of the quality of the drift-layer or the thickness of the emitter on the conductivity modulation could be excluded for the fabricated bipolar SiC-diodes of this work. Thus, it can be established that the lower emitter injection efficiency is mainly caused by the reduced electron lifetime in p-emitters formed by ion implantation. Therefore, a significant enhancement of the electron lifetime in implanted p-emitters is mandatory for e.g. SiC-MPS-diodes where the functionality of the devices depends significantly on the injection efficiency.
Available online 5 April 2018
Hot-carrier-induced Current Capability Degradation and Optimization for Lateral IGBT on Thick SOI Substrate
Publication date: Available online 11 April 2018
Source:Solid-State Electronics Author(s): Chunwei Zhang, Yang Li, Wenjing Yue, Xiaoqian Fu, Zhiming Li In this paper, the hot-carrier-induced current capability degradation of a 600V lateral insulated gate bipolar transistor (LIGBT) on thick silicon on insulator (SOI) substrate is investigated. Our experiments found that, for the SOI-LIGBT, the worst stress condition is the maximum gate voltage (V gmax) condition and the current degradation is dominated by the damages in the channel region under the V gmax stress condition. However, further analyses show that the influence of channel region damages on the collector current degradation increases with the increase of measured collector voltage and is maximum in the current saturation region. Therefore, in our opinion, the hot-carrier-induced current capability degradation of the SOI-LIGBT should be evaluated by the degradation of saturation current under the V gmax stress condition. In addition, a novel SOI-LIGBT structure with an external p-type region was also proposed, which can alleviate the damage in the channel region by reducing the lateral electric field peak. Our experimental results demonstrate that the proposed structure could optimize the hot-carrier reliability effectively with the other characteristics maintained.
April 2018
Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements
Publication date: Available online 5 April 2018
Source:Solid-State Electronics Author(s): Krishna Pradeep, Thierry Poiroux, Patrick Scheer, G
April 2018
Editorial Board
Publication date: April 2018
Source:Solid-State Electronics, Volume 142

April 2018
Application of CTLM method combining interfacial structure characterization to investigate contact formation of silver paste metallization on crystalline silicon solar cells
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Shenghu Xiong, Xiao Yuan, Hua Tong, Yunxia Yang, Cui Liu, Xiaojun Ye, Yongsheng Li, Xianhao Wang, Lan Luo Circular transmission line model (CTLM) measurements were applied to study the contact formation mechanism of the silver paste metallization on n-type emitter of crystalline silicon solar cells. The electrical performance parameters
April 2018
Role of AlGaN/GaN interface traps on negative threshold voltage shift in AlGaN/GaN HEMT
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Amit Malik, Chandan Sharma, Robert Laishram, Rajesh Kumar Bag, Dipendra Singh Rawal, Seema Vinayak, Rajesh Kumar Sharma This article reports negative shift in the threshold-voltage in AlGaN/GaN high electron mobility transistor (HEMT) with application of reverse gate bias stress. The device is biased in strong pinch-off and low drain to source voltage condition for a fixed time duration (reverse gate bias stress), followed by measurement of transfer characteristics. Negative threshold voltage shift after application of reverse gate bias stress indicates the presence of more carriers in channel as compared to the unstressed condition. We propose the presence of AlGaN/GaN interface states to be the reason of negative threshold voltage shift, and developed a process to electrically characterize AlGaN/GaN interface states. We verified the results with Technology Computer Aided Design (TCAD) ATLAS simulation and got a good match with experimental measurements.
April 2018
Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Sang Min Kim, Won Ju Cho, Chong Gun Yu, Jong Tae Park In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices.
April 2018
Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Hee Jae Chae, Ki Hwan Seok, Sol Kyu Lee, Seung Ki Joo A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.
April 2018
Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): T.A. Oproglidis, T.A. Karatsori, S. Barraud, G. Ghibaudo, C.A. Dimitriadis In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25
April 2018
Narrowing of band gap at source/drain contact scheme of nanoscale InAs–nMOS
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): A.H. Mohamed, R. Oxland, M. Aldegunde, S.P. Hepplestone, P.V. Sushko, K. Kalna A multi-scale simulation study of Ni/InAs nano-scale contact aimed for the sub-14
April 2018
Impulse response measurement in the HgCdTe avalanche photodiode
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Anand Singh, Ravinder Pal HgCdTe based mid-wave infrared focal plane arrays (MWIR FPAs) are being developed for high resolution imaging and range determination of distant camouflaged targets. Effect of bandgap grading on the response time in the n+/
April 2018
SOI MESFETs on high-resistivity, trap-rich substrates
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Payam Mehr, Xiong Zhang, William Lepkowski, Chaojiang Li, Trevor J. Thornton The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by
April 2018
Resistive RAMs as analog trimming elements
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): H. Aziza, A. Perez, J.M. Portal This work investigates the use of Resistive Random Access Memory (RRAM) as an analog trimming device. The analog storage feature of the RRAM cell is evaluated and the ability of the RRAM to hold several resistance states is exploited to propose analog trim elements. To modulate the memory cell resistance, a series of short programming pulses are applied across the RRAM cell allowing a fine calibration of the RRAM resistance. The RRAM non volatility feature makes the analog device powers up already calibrated for the system in which the analog trimmed structure is embedded. To validate the concept, a test structure consisting of a voltage reference is evaluated.
Available online 22 March 2018
Solution-processed flexible NiO resistive random access memory device
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Soo-Jung Kim, Heon Lee, Sung-Hoon Hong Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).
March 2018
Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures
Publication date: Available online 22 March 2018
Source:Solid-State Electronics Author(s): D. Boudier, B. Cretu, E. Simoen, A. Veloso, N. Collaert In this work, Gate-All-Around Nanowire MOSFETs have been studied at very low temperatures. DC behaviors have been investigated in the linear operation and saturation regions, giving access to several analog parameters. Static characteristics at 4.2
March 2018
Editorial Board
Publication date: March 2018
Source:Solid-State Electronics, Volume 141

March 2018
Surface stoichiometry modification and improved DC/RF characteristics by plasma treated and annealed AlGaN/GaN HEMTs
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Bhanu B. Upadhyay, Kuldeep Takhar, Jaya Jha, Swaroop Ganguly, Dipankar Saha We demonstrate that N2 and O2 plasma treatment followed by rapid thermal annealing leads to surface stoichiometry modification in a AlGaN/GaN high electron mobility transistor. Both the source/drain access and gate regions respond positively improving the transistor characteristics albeit to different extents. Characterizations indicate that the surface show the characteristics of that of a higher band-gap material like Al x O y and Ga x O y along with N-vacancy in the sub-surface region. The N-vacancy leads to an increased two-dimensional electron gas density. The formation of oxides lead to a reduced gate leakage current and surface passivation. The DC characteristics show increased transconductance, saturation drain current, ON/OFF current ratio, sub-threshold swing and lower ON resistance by a factor of 2.9, 2.0, 10 3.3 , 2.3, and 2.1, respectively. The RF characteristics show an increase in unity current gain frequency by a factor of 1.7 for a 500
March 2018
Normally-off AlGaN/GaN-based MOS-HEMT with self-terminating TMAH wet recess etching
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Dong-Hyeok Son, Young-Woo Jo, Chul-Ho Won, Jun-Hyeok Lee, Jae Hwa Seo, Sang-Heung Lee, Jong-Won Lim, Ji Heon Kim, In Man Kang, Sorin Cristoloveanu, Jung-Hee Lee Normally-off AlGaN/GaN-based MOS-HEMT has been fabricated by utilizing damage-free self-terminating tetramethyl ammonium hydroxide (TMAH) recess etching. The device exhibited a threshold voltage of +2.0
March 2018
Normally-off Al2O3/GaN MOSFET: Role of border traps on the device transport characteristics
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Hongyue Wang, Jinyan Wang, Jingqian Liu, Yandong He, Maojun Wang, Min Yu, Wengang Wu Based on the self-terminating gate recess technique, two different processes featuring gate-recess-first (GF) and ohmic-contact-first (OF) were proposed for E-mode Al2O3/GaN MOSFETs. Increased maximum drain current (I dmax)
March 2018
Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Yu Zhang, Lei Jin, Dandan Jiang, Xingqi Zou, Zhiguo Zhao, Jing Gao, Ming Zeng, Wenbin Zhou, Zhaoyun Tang, Zongliang Huo In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.
March 2018
A drain current model for amorphous InGaZnO thin film transistors considering temperature effects
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): M.X. Cai, R.H. Yao Temperature dependent electrical characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) are investigated considering the percolation and multiple trapping and release (MTR) conduction mechanisms. Carrier-density and temperature dependent carrier mobility in a-IGZO is derived with the Boltzmann transport equation, which is affected by potential barriers above the conduction band edge with Gaussian-like distributions. The free and trapped charge densities in the channel are calculated with Fermi-Dirac statistics, and the field effective mobility of a-IGZO TFTs is then deduced based on the MTR theory. Temperature dependent drain current model for a-IGZO TFTs is finally derived with the obtained low field mobility and free charge density, which is applicable to both non-degenerate and degenerate conductions. This physical-based model is verified by available experiment results at various temperatures.
March 2018
Advanced analytical modeling of double-gate Tunnel-FETs – A performance evaluation
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Michael Graef, Fabian Hosenfeld, Fabian Horst, Atieh Farokhnejad, Franziska Hain, Benjam
March 2018
Thermal coupling and effect of subharmonic synchronization in a system of two VO2 based oscillators
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Andrey Velichko, Maksim Belyaev, Vadim Putrolaynen, Valentin Perminov, Alexander Pergament We explore a prototype of an oscillatory neural network (ONN) based on vanadium dioxide switching devices. The model system under study represents two oscillators based on thermally coupled VO2 switches. Numerical simulation shows that the effective action radius R TC of coupling depends both on the total energy released during switching and on the average power. It is experimentally and numerically proved that the temperature change
March 2018
Improve the performance of CZTSSe solar cells by applying a SnS BSF layer
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Mir Kazem Omrani, Mehran Minbashi, Nafiseh Memarian, Dae-Hwan Kim In this study, the CZTSSe (Cu2ZnSn(S,Se)4) solar cells, with Al/ZnO:Al/ZnO (i)/CdS/CZTSSe/Mo structure, have been simulated. The simulation results have been compared and validated with real experimental results. Next, suggestions for improving the performance of CZTSSe solar cell have been provided. A SnS layer has been used as back surface field (BSF) layer. Different physical parameters of SnS layer are investigated, and the optimum values are selected. It has been found that by inserting a BSF layer with optimum parameters, the efficiency of CZTSSe solar cell increases from 12.3% to 17.25% due to enhancement of both short-circuit current density (Jsc) and open circuit voltage (Voc). For this optimized cell structure, the maximum Jsc
March 2018
Solution processed thin film transistor from liquid phase exfoliated MoS2 flakes
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Xiaoling Zeng, Hippolyte Hirwa, Sonia Metel, Valeria Nicolosi, Veit Wagner Two dimensional layers of dichalcogenide materials have attracted a lot of interests due to their potential applications in optoelectronics and energy storage. Hence, there is a large interest in establishing cheap, scalable processes for the production of low dimensional semiconducting dichalcogenide based films. In this work, well exfoliated MoS2 dispersions were prepared through a two-step liquid phase exfoliation process with N-methyl-pyrrolidone (NMP) and Isopropanol (IPA). The quality of the obtained MoS2 flakes was characterized by transmission electron microscopy, scanning electron microscopy, UV–Vis spectroscopy and Raman spectroscopy. For charge transport analysis, bottom-gate thin film transistors (TFTs) based on exfoliated MoS2 films were fabricated via spray coating technique. Electrical characterization of the obtained TFTs showed that adding a PMMA layer on top of the semiconductor lead to considerable improvements in the electrical performance. The analysis of the electrical characteristics suggests that the additional PMMA layer improves the charge transfer between adjacent flakes. Electrical measurements on TFTs with different channel length were used to separate the impact of the contact resistance and the channel resistance on the charge transport. The TFTs output curves showed non-linear current–voltage (I-V) characteristic. The non-linear behavior was attributed to the formation of Schottky barriers at the inter-flakes connection. In this work, we show a low-cost and scalable solution-based fabrication process that could boost the application of dichalcogenides in modern nanoelectronic devices.
March 2018
Enhanced transconductance in a double-gate graphene field-effect transistor
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Byeong-Woon Hwang, Hye-In Yeom, Daewon Kim, Choong-Ki Kim, Dongil Lee, Yang-Kyu Choi Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1
March 2018
X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Mingyo Park, Byung-Wook Min This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1
March 2018
Distributed parameter modeling to prevent charge cancellation for discrete thickness piezoelectric energy harvester
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): M. Krishnasamy, Feng Qian, Lei Zuo, T.R. Lenka The charge cancellation due to the change of strain along single continuous piezoelectric layer can remarkably affect the performance of a cantilever based harvester. In this paper, analytical models using distributed parameters are developed with some extent of averting the charge cancellation in cantilever piezoelectric transducer where the piezoelectric layers are segmented at strain nodes of concerned vibration mode. The electrode of piezoelectric segments are parallelly connected with a single external resistive load in the 1st model (Model 1). While each bimorph piezoelectric layers are connected in parallel to a resistor to form an independent circuit in the 2nd model (Model 2). The analytical expressions of the closed-form electromechanical coupling responses in frequency domain under harmonic base excitation are derived based on the Euler–Bernoulli beam assumption for both models. The developed analytical models are validated by COMSOL and experimental results. The results demonstrate that the energy harvesting performance of the developed segmented piezoelectric layer models is better than the traditional model of continuous piezoelectric layer.

Electrical characterization of vertically stacked p-FET SOI nanowires
Publication date: March 2018
Source:Solid-State Electronics, Volume 141 Author(s): Bruna Cardoso Paz, Mika
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