Journal Sciences News
Zoologischer Anzeiger, A Journal of Comparative Zoology
July 2018
Low voltage operation of GaN vertical nanowire MOSFET
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Dong-Hyeok Son, Young-Woo Jo, Jae Hwa Seo, Chul-Ho Won, Ki-Sik Im, Yong Soo Lee, Hwan Soo Jang, Dae-Hyun Kim, In Man Kang, Jung-Hee Lee GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300
June 2018
Numerical modeling of reverse recovery characteristic in silicon pin diodes
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Yusuke Yamashita, Hiroshi Tadano A new numerical reverse recovery model of silicon pin diode is proposed by the approximation of the reverse recovery waveform as a simple shape. This is the first model to calculate the reverse recovery characteristics using numerical equations without adjusted by fitting equations and fitting parameters. In order to verify the validity and the accuracy of the numerical model, the calculation result from the model is verified through the device simulation result.
June 2018
Editorial Board
Publication date: June 2018
Source:Solid-State Electronics, Volume 144

June 2018
Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Junjie Guo, Dingdong Xie, Bingchu Yang, Jie Jiang Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5
June 2018
Hybrid solar cells composed of perovskite and polymer photovoltaic structures
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Apatsanan Phaometvarithorn, Surawut Chuangchote, Pisist Kumnorkaew, Jatuphorn Wootthikanokkhan Organic/inorganic lead halide perovskite solar cells have recently attracted much attention in photovoltaic research, due to the devices show promising ways to achieve high efficiencies. The perovskite devices with high efficiencies, however, are typically fabricated in tandem solar cell which is complicated. In this research work, we introduce a solar cell device with the combination of CH3NH3PbI3
June 2018
A new high-
June 2018
Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Lei Qiang, Xiaoci Liang, Guangshuo Cai, Yanli Pei, Ruohe Yao, Gang Wang Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: E C
June 2018
Performance enhancement of pentacene-based organic thin-film transistors using 6,13-pentacenequinone as a carrier injection interlayer
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Ching-Lin Fan, Wei-Chun Lin, Hao-Wei Chen This work demonstrates pentacene-based organic thin-film transistors (OTFTs) fabricated by inserting a 6,13-pentacenequinone (PQ) carrier injection layer between the source/drain (S/D) metal Au electrodes and pentacene channel layer. Compared to devices without a PQ layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off current ratio were significantly improved for the device with a 5-nm-thick PQ interlayer. These improvements are attributed to significant reduction of hole barrier height at the Au/pentacene channel interfaces. Therefore, it is believed that using PQ as the carrier injection layer is a good candidate to improve the pentacene-based OTFTs electrical performance.
June 2018
A new approach to the extraction of single exponential diode model parameters
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Adelmo Ortiz-Conde, Francisco J. Garc
June 2018
The photovoltaic impact of atomic layer deposited TiO2 interfacial layer on Si-based photodiodes
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Abdulkerim Karabulut,
June 2018
Circular electrodes to reduce the current variation of OTFTs with the drop-casted semiconducting layer
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): H.M. Dipu Kabir, Zubair Ahmed, Remashan Kariyadan, Lining Zhang, Mansun Chan Circular organic thin film transistor (OTFT) structures are proposed to reduce the impact of variable grain alignment on the drive current of the polycrystalline organic thin film transistor (OTFT). As the circular structure is planar symmetric, the orientation of the grain cannot affect the drive current of the circular OTFT. Thus, circular electrodes expected to provide a lower variation. Top-gate, bottom-contact circular and conventional OTFTs with drop-casted polycrystalline 6,13-Bis(triisopropyl-silylethynyl) (TIPS)-Pentacene organic semiconducting layer (OSC) are fabricated to verify the theoretical variation reduction. The relative standard deviation (RSD), defined as the ratio of standard deviation and the average of drive current is used as the degree of variations in different structures. According to our fabrication result, circular transistors have a significantly lower variation (20% RSD), compared to the variation of conventional OTFTs (61% RSD).

### Graphical abstract

June 2018
Modeling of an 8–12
June 2018
Analysis of reverse gate leakage mechanism of AlGaN/GaN HEMTs with N2 plasma surface treatment
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Hui Liu, Zongjing Zhang, Weijun Luo The mechanism of reverse gate leakage current of AlGaN/GaN HEMTs with two different surface treatment methods are studied by using C-V, temperature dependent I–V and theoretical analysis. At the lower reverse bias region (VR
June 2018
A charge-based model of Junction Barrier Schottky rectifiers
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Alvaro D. Latorre-Rey, Mihir Mudholkar, Mohammed T. Quddus, Ali Salih A new charge-based model of the electric field distribution for Junction Barrier Schottky (JBS) diodes is presented, based on the description of the charge-sharing effect between the vertical Schottky junction and the lateral pn-junctions that constitute the active cell of the device. In our model, the inherently 2-D problem is transformed into a simple but accurate 1-D problem which has a closed analytical solution that captures the reshaping and reduction of the electric field profile responsible for the improved electrical performance of these devices, while preserving physically meaningful expressions that depend on relevant device parameters. The validation of the model is performed by comparing calculated electric field profiles with drift-diffusion simulations of a JBS device showing good agreement. Even though other fully 2-D models already available provide higher accuracy, they lack physical insight making the proposed model an useful tool for device design.
June 2018
Performance analysis and simulation of vertical gallium nitride nanowire transistors
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Bernd Witzigmann, Feng Yu, Kristian Frank, Klaas Strempel, Muhammad Fahlesa Fatahilah, Hans Werner Schumacher, Hutomo Suryo Wasisto, Friedhard R
June 2018
New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): C. Diaz Llorente, C. Le Royer, P. Batude, C. Fenouillet-Beranger, S. Martinie, C.-M.V. Lu, F. Allain, J.-P. Colinge, S. Cristoloveanu, G. Ghibaudo, M. Vinet This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.
June 2018
Graphene/black phosphorus heterostructured photodetector
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Jiao Xu, Young Jae Song, Jin-Hong Park, Sungjoo Lee Graphene photodetectors exhibit a low photoresponsivity due to their weak light absorbance. In this study, we fabricated a graphene/black phosphorus (BP) heterostructure, in which the multilayer BP flake with a
June 2018
Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Jonas Heidler, Sheng Yang, Xinliang Feng, Klaus M
June 2018
Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Yong-Jung Cho, Woo-Sic Kim, Yeol-Hyeong Lee, Jeong Ki Park, Geon Tae Kim, Ohyun Kim We investigated the mechanism of formation of the hump that occurs in the current-voltage I-V characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) that are exposed to long-term drain bias stress under illumination. Transfer characteristics showed two-stage degradation under the stress. At the beginning of the stress, the I-V characteristics shifted in the negative direction with a degradation of subthreshold slope, but the hump phenomenon developed over time in the I-V characteristics. The development of the hump was related to creation of defects, especially ionized oxygen vacancies which act as shallow donor-like states near the conduction-band minimum in a-IGZO. To further investigate the hump phenomenon we measured a capacitance-voltage C-V curve and performed two-dimensional device simulation. Stretched-out C-V for the gate-to-drain capacitance and simulated electric field distribution which exhibited large electric field near the drain side of TFT indicated that V O 2+ were generated near the drain side of TFT, but the hump was not induced when V O 2+ only existed near the drain side. Therefore, the degradation behavior under DBITS occurred because V O 2+ were created near the drain side, then were migrated to the source side of the TFT.
Available online 11 April 2018
Evidence of low injection efficiency for implanted p-emitters in bipolar 4H-SiC high-voltage diodes
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Christian D. Matthus, Andreas Huerner, Tobias Erlbacher, Anton J. Bauer, Lothar Frey In this study, the influence of the emitter efficiency on the forward current–voltage characteristics, especially the conductivity modulation of bipolar SiC-diodes was analyzed. It was determined that the emitter efficiency of p-emitters formed by ion implantation is significantly lower compared to p-emitters formed by epitaxy. In contrast to comparable studies, experimental approach was arranged that the influence of the quality of the drift-layer or the thickness of the emitter on the conductivity modulation could be excluded for the fabricated bipolar SiC-diodes of this work. Thus, it can be established that the lower emitter injection efficiency is mainly caused by the reduced electron lifetime in p-emitters formed by ion implantation. Therefore, a significant enhancement of the electron lifetime in implanted p-emitters is mandatory for e.g. SiC-MPS-diodes where the functionality of the devices depends significantly on the injection efficiency.
Available online 5 April 2018
Hot-carrier-induced Current Capability Degradation and Optimization for Lateral IGBT on Thick SOI Substrate
Publication date: Available online 11 April 2018
Source:Solid-State Electronics Author(s): Chunwei Zhang, Yang Li, Wenjing Yue, Xiaoqian Fu, Zhiming Li In this paper, the hot-carrier-induced current capability degradation of a 600V lateral insulated gate bipolar transistor (LIGBT) on thick silicon on insulator (SOI) substrate is investigated. Our experiments found that, for the SOI-LIGBT, the worst stress condition is the maximum gate voltage (V gmax) condition and the current degradation is dominated by the damages in the channel region under the V gmax stress condition. However, further analyses show that the influence of channel region damages on the collector current degradation increases with the increase of measured collector voltage and is maximum in the current saturation region. Therefore, in our opinion, the hot-carrier-induced current capability degradation of the SOI-LIGBT should be evaluated by the degradation of saturation current under the V gmax stress condition. In addition, a novel SOI-LIGBT structure with an external p-type region was also proposed, which can alleviate the damage in the channel region by reducing the lateral electric field peak. Our experimental results demonstrate that the proposed structure could optimize the hot-carrier reliability effectively with the other characteristics maintained.
April 2018
Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements
Publication date: Available online 5 April 2018
Source:Solid-State Electronics Author(s): Krishna Pradeep, Thierry Poiroux, Patrick Scheer, G
April 2018
Editorial Board
Publication date: April 2018
Source:Solid-State Electronics, Volume 142

April 2018
Application of CTLM method combining interfacial structure characterization to investigate contact formation of silver paste metallization on crystalline silicon solar cells
Publication date: April 2018
Source:Solid-State Electronics, Volume 142 Author(s): Shenghu Xiong, Xiao Yuan, Hua Tong, Yunxia Yang, Cui Liu, Xiaojun Ye, Yongsheng Li, Xianhao Wang, Lan Luo Circular transmission line model (CTLM) measurements were applied to study the contact formation mechanism of the silver paste metallization on n-type emitter of crystalline silicon solar cells. The electrical performance parameters