Journal Sciences News
Zoologischer Anzeiger, A Journal of Comparative Zoology
September 2018
Ti/Al/Ti/TiW Au-free low temperature ohmic contacts for un-doped AlGaN/GaN HEMTs
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Qixin Li, Quanbin Zhou, Sheng Gao, Xiaoyi Liu, Hong Wang We demonstrated an Au-free ohmic contact for un-doped AlGaN/GaN HEMTs with Ti/Al/Ti/TiW metal structure. The Au-free ohmic contact was fabricated by pre-ohmic recess etching and low annealing temperature. The contact characteristics of the Ti/Al/Ti/TiW Au-free ohmic contacts including current-voltage, contact resistivity, and microstructure are systematically investigated. The contact resistivity of Ti/Al/Ti/TiW ohmic contact with 22-nm recessed depth and 600
September 2018
A review on terahertz photogalvanic spectroscopy of Bi2Te3- and Sb2Te3-based three dimensional topological insulators
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Helene Plank, Sergey D. Ganichev The paper overviews experimental and theoretical studies of photogalvanic effects induced in BiSbTe-based three dimensional topological insulators by polarized terahertz radiation. We present the state-of-the-art of this subject, including most recent and well-established results. We discuss a phenomenological theory based on symmetry arguments and models illustrating the photocurrents origin. We give a brief glimpse of the underlying microscopic theory, as well as an overview of the main experimental results.
September 2018
Effect of MgO doping on the BiVO4 sensing electrode performance for YSZ-based potentiometric ammonia sensor
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Chao Wang, Jinlong Xu, Bin Yang, Feng Xia, Yiwei Zhu, Jianzhong Xiao In order to improve the microstructure and sensing property for electrode material BiVO4 of potentiometric ammonia sensor, different MgO-doped (0, 1, 3, 5 and 8
September 2018
Enlarged memory margins for resistive switching devices based on polyurethane film due to embedded Ag nanoparticles
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Lu Liu, Kailei Lu, Dong Yan, Jiazhen Zhang, Chi Ma, Zhengqiang Jia, Wen Wang, Enming Zhao Current-voltage (I-V) properties of indium-tin-oxide/Ag nanoparticles embedded in polyurethane film/Al devices exhibited a current bistability with ON/OFF ratio within the range of 105103 with the variation of voltage from
September 2018
Lumped-element model of plasmonic solar cells
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Chang-Hyun Kim, Maria Seitanidou, Jong Woo Jin, Yvan Bonnassieux, Gilles Horowitz, Ioannis Vangelidis, Elefterios Lidorikis, Argiris Laskarakis, Stergios Logothetidis Although metallic nanostructures in solar cells provide versatility in designing useful plasmonic architectures, understanding is still limited on how to exploit their multi-scale contribution as tunable performance. In this article, we suggest a characteristic model that develops into a simple and robust tool for guiding optimization of plasmonic solar devices. The model is conceptually based on the breakdown of the active region into intrinsic and plasmonic sub-circuits, by which the terminal currents are directly correlated with particle geometries and local improvement. Measurements from organic cells support the validity of our theory, and a series of simulation provides further insights into the critical trade-off between voltage and current generation, finally offering a strategy for efficiency enhancement.
September 2018
Device behaviour and zero temperature coefficients analysis for microwave GaAs HEMT
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Mohammad A. Alim, Ali A. Rezazadeh Detailed analysis of device behaviour on the zero-temperature coefficient (ZTC) points for microwave GaAs based high-electron mobility transistor is presented by means of on-wafer measurements over the temperatures between
September 2018
Analytical modeling of metal gate granularity based threshold voltage variability in NWFET
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): P. Harsha Vardhan, Sushant Mittal, Swaroop Ganguly, Udayan Ganguly Estimation of threshold voltage V T variability for NWFETs has been computationally expensive due to lack of analytical models. Variability estimation of NWFET is essential to design the next generation logic circuits. Compared to any other process induced variabilities, Metal Gate Granularity (MGG) is of paramount importance due to its large impact on V T variability. Here, an analytical model is proposed to estimate V T variability caused by MGG. We extend our earlier FinFET based MGG model to a cylindrical NWFET by satisfying three additional requirements. First, the gate dielectric layer is replaced by Silicon of electro-statically equivalent thickness using long cylinder approximation; Second, metal grains in NWFETs satisfy periodic boundary condition in azimuthal direction; Third, electrostatics is analytically solved in cylindrical polar coordinates with gate boundary condition defined by MGG. We show that quantum effects only shift the mean of the V T distribution without significant impact on the variability estimated by our electrostatics-based model. The V T distribution estimated by our model matches TCAD simulations. The model quantitatively captures grain size dependence with
August 2018
Effect of two-dimensional electron gas on horizontal heat transfer in AlGaN/AlN/GaN heterojunction transistors
Publication date: September 2018
Source:Solid-State Electronics, Volume 147 Author(s): Xiang Zheng, Shiwei Feng, Yamin Zhang, Yunpeng Jia We propose a specialized gate-drain separation structure for use in investigation of the dynamic behavior of the thermal transport characteristics in AlGaN/AlN/GaN heterojunction transistors. Using this structure, the influence of the two-dimensional electron gas (2DEG) on the horizontal heat transfer in these transistors was identified experimentally. A temperature delay (i.e., the difference in temperature at the same time) of 1.3
August 2018
Editorial Board
Publication date: August 2018
Source:Solid-State Electronics, Volume 146

August 2018
Digital and analog TFET circuits: Design and benchmark
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): S. Strangio, F. Settino, P. Palestri, M. Lanuzza, F. Crupi, D. Esseni, L. Selmi In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10
August 2018
A novel empirical I-V model for GaN HEMTs
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Jie Yang, Yeting Jia, Ning Ye, Shuo Gao In this paper, a novel eight-parameter empirical nonlinear current-voltage (I-V) model for gallium nitride (GaN) high electron mobility transistors (HEMTs) is presented. A hyperbolic sine function is introduced in this model to describe the transfer characteristics between drain-source current, Ids , and gate-source voltage, Vgs . The self-heating and trapping effects have been considered and incorporated into the proposed model through expansion parameters. The proposed model has been verified on four different types of GaN HEMTs with good agreements between the simulated curves and the measured data. Comparison between the proposed model and other traditional non-square-law models indicates a significant accuracy improvement especially in linear region by the proposed model. This simple but accurate empirical I-V model can be easily implemented for computer aided circuit design and simulation with GaN HEMTs.
August 2018
High speed terahertz modulator based on the single channel AlGaN/GaN high electron mobility transistor
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Xiaoyu Zhang, Yuanyuan Xing, Qiang Zhang, Yanping Gu, Yao Su, Chunlan Ma We demonstrate an electrically tunable terahertz (THz) modulator based on the single channel AlGaN/GaN high electrons mobility transistor (HEMT). HEMT integrated in the modulator structures is used to change the conductance of the modulator by the applied gate voltage Vg . Under the radiation of THz electromagnetic wave, the change of THz transmissivity through the modulator can be controlled by Vg . The THz modulation depth shows about 33% at the working frequency of 0.835 THz under the DC voltage Vg
August 2018
Terahertz response of a field-effect transistor loaded with a reactive component
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Abdel Majid Mammeri, Fatima Zohra Mahi, Hugues Marinchio, Cristophe Palermo, Luca Varani A study of the small-signal response of a Field-Effect Transistor connected to a purely reactive load is proposed. In particular, this model, using the equivalent admittances approach, is applied to a transistor connected to an inductance L, a capacitance C and LC resonant and anti-resonant circuits. The influence of such frequency-dependent load on the dynamics of the transistor, dominated in the terahertz range by collective plasma behavior, is investigated. This leads to the possibilities of shifting, amplifying or softening resonances appearing in the voltage gain spectrum. The effect of a resistive part of the load is also estimated.
August 2018
Research of the SPiN diodes for silicon-based reconfigurable holographic antenna
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Han Su, Huiyong Hu, Bin Shu, Bin Wang, Wei Wang, Jiaxiang Wang Silicon-based solid state plasma antennas were characterized by its wide radiation range, good stealth characteristic, and dynamic reconfigurability, which have broad application prospects in the future. In this paper, investigations of surface PiN diodes developed for silicon-based reconfigurable holographic antennas have been demonstrated for using millimeter-wave communication systems. The SPiN diodes have been extensively discussed, and the obtained results (simulations and experiments) confirm the applicability of these devices for dynamically reconfigurable antennas. A carrier concentration of 10181019
August 2018
Theoretical analysis of the charge collection at a nano-Schottky contact
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Abdelillah El Hdiy A theoretical analysis of the current collected in semiconductors in the electron beam induced current technique in the case of a nano-Schottky contact is given. The electron beam is in normal incidence and the surface recombination velocity is taken to be equal to zero. The analysis is based on the use of new boundary conditions imposed by the nano-scale size and shape of the electrode. Different expressions of the induced current are obtained from the diffusion equation as a function of polar coordinates, and their reliability are analyzed for the purpose of describing the induced current profiles which can be used for the determination of the minority carrier diffusion length. All expressions of the current depend on the nano-contact size, which has a great importance in the charge collection process, but not on nano-contact area.
August 2018
Improvement of cell reliability by floating gate implantation on 1Xnm NAND flash memory
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Jeng-Hwa Liao, Zong-Jie Ko, Yu-Min Lin, Hsing-Ju Lin, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu Continuous scaling down NAND flash memory toward below 1Xnm node generation will result in serious floating gate (FG) poly depletion and significantly impact the cell reliability performance. In this study, the FG implantation before inter-poly-dielectric deposition was proposed. We have successfully explored the methods to minimize the FG implanted damage issue and hence the void-free control gate (CG) can be achieved after the CG poly-Si fill-in. After optimizing the FG implanted processes, the cell reliabilities on 1Xnm NAND flash device were verified. The FG poly depletion can be effectively reduced by the additional FG dopant, which results in the significant improvement on the natural threshold-voltage (Vt ) distribution width, the program noise, and the program/erase Vt degradation. Moreover, there is no degradation on non-cycle data retention when adding the FG implantation, which suggests no extra FG dopant penetrated into tunnel oxide as the trap sites to enhance the trap-assisted tunneling leakage under high temperature baking.
July 2018
Investigation of nonlinear distortion in double heterojunction GaAs based pHEMT subject to frequency and temperature
Publication date: August 2018
Source:Solid-State Electronics, Volume 146 Author(s): Mohammad A. Alim, Mayahsa M. Ali, Ali A. Rezazadeh Linear and nonlinear characteristics of a 0.5
July 2018
Editorial Board
Publication date: July 2018
Source:Solid-State Electronics, Volume 145

July 2018
Effect of substrate thinning on the electronic transport characteristics of AlGaN/GaN HEMTs
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Hui Zhu, Xiao Meng, Xiang Zheng, Ying Yang, Shiwei Feng, Yamin Zhang, Chunsheng Guo We studied how substrate thinning affected the electronic transport characteristics of AlGaN/GaN HEMTs. By thinning their sapphire substrate from 460
July 2018
Low voltage operation of GaN vertical nanowire MOSFET
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Dong-Hyeok Son, Young-Woo Jo, Jae Hwa Seo, Chul-Ho Won, Ki-Sik Im, Yong Soo Lee, Hwan Soo Jang, Dae-Hyun Kim, In Man Kang, Jung-Hee Lee GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300
July 2018
Numerical modeling of reverse recovery characteristic in silicon pin diodes
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Yusuke Yamashita, Hiroshi Tadano A new numerical reverse recovery model of silicon pin diode is proposed by the approximation of the reverse recovery waveform as a simple shape. This is the first model to calculate the reverse recovery characteristics using numerical equations without adjusted by fitting equations and fitting parameters. In order to verify the validity and the accuracy of the numerical model, the calculation result from the model is verified through the device simulation result.
July 2018
Tunable-Sensitivity flexible pressure sensor based on graphene transparent electrode
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Shi Luo, Jun Yang, Xuefen Song, Xi Zhou, Leyong Yu, Tai Sun, Chongsheng Yu, Deping Huang, Chunlei Du, Dapeng Wei Tunable-sensitivity and flexibility are considered as two crucial characteristics for future pressure sensors or electronic skins. By the theoretical calculation model, we simulated the relationship curve between the sensitivity and PDMS pyramids with different spacings, and found that the spacing of pyramids is a main factor to affect the sensitivity of the capacitance pressure sensor. Furthermore, we fabricated the capacitance pressure sensors using graphene electrodes and the PDMS pyramid dielectric layers with different spacings. The measurement data were consistent with the simulation results that the sensitivity increases with the spacing of pyramids. In addition, graphene electrode exhibits prefect flexibility and reliability, while the ITO electrode would be destroyed rapidly after bending. These graphene pressure sensors exhibit the potential in the application in the wearable products for monitoring breath, pulse, and other physiological signals.
July 2018
Hot-carrier-induced current capability degradation and optimization for lateral IGBT on thick SOI substrate
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Chunwei Zhang, Yang Li, Wenjing Yue, Xiaoqian Fu, Zhiming Li In this paper, the hot-carrier-induced current capability degradation of a 600
July 2018
Light-controlled resistive switching characteristics in ZnO/BiFeO3/ZnO thin film
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Dandan Liang, Xiaoping Li, Junshuai Wang, Liangchen Wu, Peng Chen ZnO/BiFeO3/ZnO multilayer was fabricated on silicon (Si) substrate by radio-frequency magnetron sputtering system. The resistive switching characteristics in ZnO/BiFeO3/ZnO devices are observed, and the resistive switching behavior can be modulated by white light.
July 2018
Effect of traps on the charge transport in semiconducting polymer PCDTBT
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Mohd Taukeer Khan, Vikash Agrawal, Abdullah Almohammedi, Vinay Gupta Organic semiconductors (OSCs) are nowadays called upon as promising candidates for next generation electronics devices. Due to disorder structure of these materials, a high density of traps are present in their energy band gap which affect the performance of these devices. In the present manuscript, we have investigated the role of traps on charge transport in PCDTBT thin film by measuring the temperature dependent J(V) characteristics in hole only device configuration. The obtained results were analyzed by space charge limited (SCL) conduction model. It has been found that the room temperature J(V) characteristics follow Mott-Gurney square law for trap-free SCL conduction. But below 278
Available online 18 June 2018
Performances of two-finger stacked fin quinary indium gallium zinc aluminum oxide thin-film transistors
Publication date: July 2018
Source:Solid-State Electronics, Volume 145 Author(s): Li-Yi Jian, Hsin-Ying Lee, Yung-Hao Lin, Ching-Ting Lee The two-finger stacked bottom gate and top gate fin indium gallium zinc aluminum oxide thin-film transistors (IGZAO TFTs) were fabricated. Since the bottom induced channel layer and the top induced channel layer were formed in the stacked TFTs using the bottom gate and the top gate, simultaneously. Consequently, drain-source current and transconductance of the stacked TFTs were enhanced about twice as those of the bottom gate TFTs and the top gate TFTs. The optimal performances of the stacked TFTs could be obtained, when the whole channel layer was induced as the carrier transportation path.
Available online 7 June 2018
Physical Origin of the Non-Linearity in Amorphous In-Ga-Zn-O Thin-Film Transistor Current-Voltage Characteristics
Publication date: Available online 18 June 2018
Source:Solid-State Electronics Author(s): Bo-Wei Chen, Eric K. Yu, Ting-Chang Chang, Jerzy Kanicki The amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) current voltage (I-V) characteristics can be significantly distorted by either series resistance, RS , associated with the source/drain (S/D) contact regions or/and density of states. To isolate Rs contribution we used the five terminals coplanar homojunction TFT structure. Experimental results have shown this device structure has a low S/D contact resistance that do not contribute to observed I-V nonlinearity. We have shown using combination of the experimental data and two- dimensional simulations that the observed nonlinearity can be associated with the conduction band-tail states.
Available online 5 June 2018
System-level Read Disturb Suppression Techniques of TLC NAND Flash Memories for Read-Hot/Cold Data Mixed Applications
Publication date: Available online 7 June 2018
Source:Solid-State Electronics Author(s): Hikaru Watanabe, Yoshiaki Deguchi, Atsuro Kobayashi, Chihiro Matsui, Ken Takeuchi In this paper, versatile triple-level cell (TLC) NAND flash memory control with four proposed techniques, Read-Hot/Cold Migration, Read Voltage Control (RVC), Edge Word-Line Protection (EWLP), and Worst Page Detection (WPD), is proposed for data center application solid-state drives (SSDs). To apply the optimal reliability enhancement techniques for stored data, first proposal of Read-Hot/Cold Migration separates read-hot/cold data into each region. Then, second proposal, Read Voltage Control applies the optimal read reference voltages (V REF) for each read-hot/cold region to improve the overall reliability of TLC NAND flash. Third proposal, Edge Word-Line Protection reduces the bit error rate (BER) of the edge word-lines (WLs), which have the worst reliability in read-hot data as reported in this paper. Finally, Worst Page Detection is proposed to predict the worst page BER in a block precisely to prevent judging entire block as bad and optimizes the refresh interval of read-hot block. By combining all of these techniques, the reliability of TLC NAND flash is enhanced for both read-hot and cold data.
June 2018
Editorial Board
Publication date: June 2018
Source:Solid-State Electronics, Volume 144

June 2018
Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Junjie Guo, Dingdong Xie, Bingchu Yang, Jie Jiang Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5
June 2018
Hybrid solar cells composed of perovskite and polymer photovoltaic structures
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Apatsanan Phaometvarithorn, Surawut Chuangchote, Pisist Kumnorkaew, Jatuphorn Wootthikanokkhan Organic/inorganic lead halide perovskite solar cells have recently attracted much attention in photovoltaic research, due to the devices show promising ways to achieve high efficiencies. The perovskite devices with high efficiencies, however, are typically fabricated in tandem solar cell which is complicated. In this research work, we introduce a solar cell device with the combination of CH3NH3PbI3
June 2018
A new high-
June 2018
Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Lei Qiang, Xiaoci Liang, Guangshuo Cai, Yanli Pei, Ruohe Yao, Gang Wang Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: E C
June 2018
Performance enhancement of pentacene-based organic thin-film transistors using 6,13-pentacenequinone as a carrier injection interlayer
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Ching-Lin Fan, Wei-Chun Lin, Hao-Wei Chen This work demonstrates pentacene-based organic thin-film transistors (OTFTs) fabricated by inserting a 6,13-pentacenequinone (PQ) carrier injection layer between the source/drain (S/D) metal Au electrodes and pentacene channel layer. Compared to devices without a PQ layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off current ratio were significantly improved for the device with a 5-nm-thick PQ interlayer. These improvements are attributed to significant reduction of hole barrier height at the Au/pentacene channel interfaces. Therefore, it is believed that using PQ as the carrier injection layer is a good candidate to improve the pentacene-based OTFTs electrical performance.
June 2018
A new approach to the extraction of single exponential diode model parameters
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Adelmo Ortiz-Conde, Francisco J. Garc
June 2018
The photovoltaic impact of atomic layer deposited TiO2 interfacial layer on Si-based photodiodes
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Abdulkerim Karabulut,
June 2018
Circular electrodes to reduce the current variation of OTFTs with the drop-casted semiconducting layer
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): H.M. Dipu Kabir, Zubair Ahmed, Remashan Kariyadan, Lining Zhang, Mansun Chan Circular organic thin film transistor (OTFT) structures are proposed to reduce the impact of variable grain alignment on the drive current of the polycrystalline organic thin film transistor (OTFT). As the circular structure is planar symmetric, the orientation of the grain cannot affect the drive current of the circular OTFT. Thus, circular electrodes expected to provide a lower variation. Top-gate, bottom-contact circular and conventional OTFTs with drop-casted polycrystalline 6,13-Bis(triisopropyl-silylethynyl) (TIPS)-Pentacene organic semiconducting layer (OSC) are fabricated to verify the theoretical variation reduction. The relative standard deviation (RSD), defined as the ratio of standard deviation and the average of drive current is used as the degree of variations in different structures. According to our fabrication result, circular transistors have a significantly lower variation (20% RSD), compared to the variation of conventional OTFTs (61% RSD).

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June 2018
Analysis of reverse gate leakage mechanism of AlGaN/GaN HEMTs with N2 plasma surface treatment
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Hui Liu, Zongjing Zhang, Weijun Luo The mechanism of reverse gate leakage current of AlGaN/GaN HEMTs with two different surface treatment methods are studied by using C-V, temperature dependent IV and theoretical analysis. At the lower reverse bias region (VR
June 2018
A charge-based model of Junction Barrier Schottky rectifiers
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Alvaro D. Latorre-Rey, Mihir Mudholkar, Mohammed T. Quddus, Ali Salih A new charge-based model of the electric field distribution for Junction Barrier Schottky (JBS) diodes is presented, based on the description of the charge-sharing effect between the vertical Schottky junction and the lateral pn-junctions that constitute the active cell of the device. In our model, the inherently 2-D problem is transformed into a simple but accurate 1-D problem which has a closed analytical solution that captures the reshaping and reduction of the electric field profile responsible for the improved electrical performance of these devices, while preserving physically meaningful expressions that depend on relevant device parameters. The validation of the model is performed by comparing calculated electric field profiles with drift-diffusion simulations of a JBS device showing good agreement. Even though other fully 2-D models already available provide higher accuracy, they lack physical insight making the proposed model an useful tool for device design.
June 2018
Performance analysis and simulation of vertical gallium nitride nanowire transistors
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Bernd Witzigmann, Feng Yu, Kristian Frank, Klaas Strempel, Muhammad Fahlesa Fatahilah, Hans Werner Schumacher, Hutomo Suryo Wasisto, Friedhard R
June 2018
New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube integration
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): C. Diaz Llorente, C. Le Royer, P. Batude, C. Fenouillet-Beranger, S. Martinie, C.-M.V. Lu, F. Allain, J.-P. Colinge, S. Cristoloveanu, G. Ghibaudo, M. Vinet This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.
June 2018
Graphene/black phosphorus heterostructured photodetector
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Jiao Xu, Young Jae Song, Jin-Hong Park, Sungjoo Lee Graphene photodetectors exhibit a low photoresponsivity due to their weak light absorbance. In this study, we fabricated a graphene/black phosphorus (BP) heterostructure, in which the multilayer BP flake with a
June 2018
Ferroelectric field-effect transistors based on solution-processed electrochemically exfoliated graphene
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Jonas Heidler, Sheng Yang, Xinliang Feng, Klaus M
June 2018
Effect of defect creation and migration on hump characteristics of a-InGaZnO thin film transistors under long-term drain bias stress with light illumination
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Yong-Jung Cho, Woo-Sic Kim, Yeol-Hyeong Lee, Jeong Ki Park, Geon Tae Kim, Ohyun Kim We investigated the mechanism of formation of the hump that occurs in the current-voltage I-V characteristics of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) that are exposed to long-term drain bias stress under illumination. Transfer characteristics showed two-stage degradation under the stress. At the beginning of the stress, the I-V characteristics shifted in the negative direction with a degradation of subthreshold slope, but the hump phenomenon developed over time in the I-V characteristics. The development of the hump was related to creation of defects, especially ionized oxygen vacancies which act as shallow donor-like states near the conduction-band minimum in a-IGZO. To further investigate the hump phenomenon we measured a capacitance-voltage C-V curve and performed two-dimensional device simulation. Stretched-out C-V for the gate-to-drain capacitance and simulated electric field distribution which exhibited large electric field near the drain side of TFT indicated that V O 2+ were generated near the drain side of TFT, but the hump was not induced when V O 2+ only existed near the drain side. Therefore, the degradation behavior under DBITS occurred because V O 2+ were created near the drain side, then were migrated to the source side of the TFT.

Evidence of low injection efficiency for implanted p-emitters in bipolar 4H-SiC high-voltage diodes
Publication date: June 2018
Source:Solid-State Electronics, Volume 144 Author(s): Christian D. Matthus, Andreas Huerner, Tobias Erlbacher, Anton J. Bauer, Lothar Frey In this study, the influence of the emitter efficiency on the forward currentvoltage characteristics, especially the conductivity modulation of bipolar SiC-diodes was analyzed. It was determined that the emitter efficiency of p-emitters formed by ion implantation is significantly lower compared to p-emitters formed by epitaxy. In contrast to comparable studies, experimental approach was arranged that the influence of the quality of the drift-layer or the thickness of the emitter on the conductivity modulation could be excluded for the fabricated bipolar SiC-diodes of this work. Thus, it can be established that the lower emitter injection efficiency is mainly caused by the reduced electron lifetime in p-emitters formed by ion implantation. Therefore, a significant enhancement of the electron lifetime in implanted p-emitters is mandatory for e.g. SiC-MPS-diodes where the functionality of the devices depends significantly on the injection efficiency.
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