Journal Sciences News
Zoologischer Anzeiger, A Journal of Comparative Zoology
January 2018
Editorial Board
Publication date: January 2018
Source:Solid-State Electronics, Volume 139

January 2018
Investigation of surface PiN diodes for a novel reconfigurable antenna
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Han Su, Huiyong Hu, Heming Zhang, Bin Wang, Haiyan Kang, Yu Wang, Minru Hao In this paper, investigations of surface PiN diodes developed for a reconfigurable plasma antenna have been described. To increase carrier concentration within the surface PiN diodes as much as possible, parameters of the plasma region have been extensively discussed. According to these studies, it has been found that the average carrier concentration within the ‘i’ region has been achieved the level of 1018
January 2018
A terahertz performance of hybrid single walled CNT based amplifier with analytical approach
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Sandeep Kumar, Hanjung Song This work is focuses on terahertz performance of hybrid single walled carbon nanotube (CNT) based amplifier and proposed for measurement of soil parameters application. The proposed circuit topology provides hybrid structure which achieves wide impedance bandwidth of 0.33
January 2018
Modeling of thermal coupling in VO2-based oscillatory neural networks
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Andrey Velichko, Maksim Belyaev, Vadim Putrolaynen, Valentin Perminov, Alexander Pergament In this study, we have demonstrated the possibility of using the thermal coupling to control the dynamics of operation of coupled VO2 oscillators. Based on the example of a ‘switch-microheater’ pair, we have explored the synchronization and dissynchronization modes of a single oscillator with respect to an external harmonic heat impact. The features of changes in the spectra are shown, in particular, the effect of the natural frequency attraction to the affecting signal frequency and the self-oscillation noise reduction effects at synchronization. The time constant of the temperature effect for the considered system configuration is in the range 7–140
January 2018
Investigation on the variation of channel resistance and contact resistance of SiZnSnO semiconductor depending on Si contents using transmission line method
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Byeong Hyeon Lee, Sangmin Han, Sang Yeol Lee Amorphous silicon-zinc-tin-oxide (a-SZTO) thin film transistors (TFTs) have been fabricated depending on the silicon ratio in channel layers. The a-SZTO TFT exhibited high electrical properties, such as high mobility of 23cm2 V
January 2018
Palladium (Pd) sensitized molybdenum trioxide (MoO3) nanobelts for nitrogen dioxide (NO2) gas detection
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): A.A. Mane, A.V. Moholkar The MoO3 nanobelts have been grown onto the glass substrates using chemical spray pyrolysis (CSP) deposition technique at optimized substrate temperature of 400°C. XRD study shows that the film is polycrystalline in nature and possesses an orthorhombic crystal structure. The FE-SEM micrographs show the formation of nanobelts-like morphology of MoO3. The presence of Pd and its oxidation states in Pd-sensitized MoO3 film is confirmed using EDAX and XPS study, respectively. The percentage gas response is defined as | R g - R a | R a
January 2018
Accurate diode behavioral model with reverse recovery
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Stanislav Ban
January 2018
Design optimization and fabrication of a novel structural piezoresistive pressure sensor for micro-pressure measurement
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Chuang Li, Francisco Cordovilla, Jos
January 2018
The feasibility of using solution-processed aqueous La2O3 as effective hole injection layer in organic light-emitting diode
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Yan Zhang, Wanshu Li, Ting Zhang, Bo Yang, Qinghong Zheng, Jiwen Xu, Hua Wang, Lihui Wang, Xiaowen Zhang, Bin Wei Low-cost and scalable manufacturing boosts organic electronic devices with all solution process. La2O3 powders and corresponding aqueous solutions are facilely synthesized. Atomic force microscopy and scanning electron microscopy measurements show that solution-processed La2O3 behaves superior film morphology. X-ray diffraction and X-ray photoelectron spectroscopy measurements verify crystal phase and typical La signals. In comparison with the most widely-used hole injection layers (HILs) of MoOx and poly(ethylene dioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), enhanced luminous efficiency is observed in organic light-emitting diode (OLED) using solution-processed La2O3 HIL. Current-voltage, impedance-voltage and phase angle-voltage transition curves clarify that solution-processed La2O3 behaves nearly comparable hole injection capacity to MoOx and PEDOT:PSS, and favorably tailors carrier balance. Moreover, the hole injection mechanism of solution-processed La2O3 is proven to be predominantly controlled by Fowler-Nordheim tunneling process and the hole injection barrier height between ITO and NPB via La2O3 interlayer is estimated to be 0.098
January 2018
A 32
January 2018
ESD robustness improving for the low-voltage triggering silicon-controlled rectifier by adding NWell at cathode
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Xiangliang Jin, Yifei Zheng, Yang Wang, Jian Guan, Shanwan Hao, Kan Li, Jun Luo The low-voltage triggering silicon-controlled rectifier (LVTSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its low trigger voltage and strong current-tolerating capability per area. In this paper, an improved LVTSCR by adding a narrow NWell (NW2) under the source region of NMOS is discussed, which is realized in a 0.5-
January 2018
Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Amin M. Saleem, Rickard Andersson, Vincent Desmaris, Peter Enoksson Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5
January 2018
Assessment of intrinsic small signal parameters of submicron SiC MESFETs
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Mohammad Riaz, Muhammad Mansoor Ahmed, Umair Rafique, Umer Farooq Ahmed In this paper, a technique has been developed to estimate intrinsic small signal parameters of submicron SiC MESFETs, designed for high power microwave applications. In the developed technique, small signal parameters are extracted by involving drain-to-source current, I ds instead of Schottky barrier depletion layer expression. It has been demonstrated that in SiC MESFETs, the depletion layer gets modified due to intense transverse electric field and/or self-heating effects, which are conventionally not taken into account. Thus, assessment of AC small signal parameters by employing depletion layer expression loses its accuracy for devices meant for high power applications. A set of expressions for AC small signal elements has been developed using I ds and its dependence on device biasing has been discussed. The validity of the proposed technique has been demonstrated using experimental data.
January 2018
Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): B. Mohamad, C. Leroux, G. Reimbold, G. Ghibaudo For advanced gate stacks, effective work function (WFeff) and equivalent oxide thickness (EOT) are fundamental parameters for technology optimization. On FDSOI transistors, and contrary to the bulk technologies, while EOT can still be extracted at strong inversion from the typical gate-to-channel capacitance (Cgc), it is no longer the case for WFeff due to the disappearance of an observable flat band condition on capacitance characteristics. In this work, a new experimental method, the Cbg(VBG) characteristic, is proposed in order to extract the well flat band condition (VFB, W). This characteristic enables an accurate and direct evaluation of WFeff. Moreover, using the previous extraction of the gate oxide (tfox), and buried oxide (tbox) from typical capacitance characteristics (Cgc and Cbc), it allows the extraction of the channel thickness (tch). Furthermore, the measurement of the well flat band condition on Cbg(VBG) characteristics for two different Si and SiGe channel also proves the existence of a dipole at the SiGe/SiO2 interface.
January 2018
MEMS fabrication and frequency sweep for suspending beam and plate electrode in electrostatic capacitor
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Jianxiong Zhu, Weixing Song We report a MEMS fabrication and frequency sweep for a high-order mode suspending beam and plate layer in electrostatic micro-gap semiconductor capacitor. This suspended beam and plate was designed with silicon oxide (SiO2) film which was fabricated using bulk silicon micromachining technology on both side of a silicon substrate. The designed semiconductor capacitors were driven by a bias direct current (DC) and a sweep frequency alternative current (AC) in a room temperature for an electrical response test. Finite element calculating software was used to evaluate the deformation mode around its high-order response frequency. Compared a single capacitor with a high-order response frequency (0.42
January 2018
Wigner transport simulation of (core gate) silicon-shell nanowire transistors in cylindrical coordinates
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Joon-Ho Lee, Woo Jin Jeong, Junbeom Seo, Mincheol Shin Gate-all-around silicon nanowire transistors (SNWTs) are recognized as promising candidates to reduce problems due to quantum effects in conventional nano-transistors. In this study we investigate whether structural modification of SNWTs leads to improved performance. A model calculation for a transistor with a channel length of several nanometers requires a quantum transport simulator, and we use a Wigner transport equation (WTE) discretized by a third-order upwind differential scheme (TDS) suggested by Yamada et al. (2009) for quantum transport simulations of gate-all-around silicon-shell nanowire transistors (SSNWTs), core gate SSNWTs (CG-SSNWTs), and independent CG-SSNWTs (ICG-SSNWTs). A WTE discretized by the TDS is known to produce highly accurate results. The SSNWT has a structure in which an insulator cylinder is inserted into the center axis of the SNWT, and the CG-SSNWT has a structure in which a core gate is inserted into the center axis of the SSNWT. The calculations show that the performances of the SSNWTs are improved by introducing the Si-shell structure and the core gate. The ICG-SSNWTs are identical in structure to the CG-SSNWTs, but the outer and core gates are independently biased. The calculations for the ICG-SSNWTs show that the threshold voltage can be controlled using the difference between the core and outer gate voltages.
January 2018
Effects of phosphorus on the electrical characteristics of plasma deposited hydrogenated amorphous silicon carbide thin films
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Burak Alcinkaya, Kivanc Sel The properties of phosphorus doped hydrogenated amorphous silicon carbide (a-SiCx:H) thin films, that were deposited by plasma enhanced chemical vapor deposition technique with four different carbon contents (x), were analyzed and compared with those of the intrinsic a-SiCx:H thin films. The carbon contents of the films were determined by X-ray photoelectron spectroscopy. The thickness and optical energies, such as Tauc, E04 and Urbach energies, of the thin films were determined by UV–Visible transmittance spectroscopy. The electrical properties of the films, such as conductivities and activation energies were analyzed by temperature dependent current–voltage measurements. Finally, the conduction mechanisms of the films were investigated by numerical analysis, in which the standard transport mechanism in the extended states and the nearest neighbor hopping mechanism in the band tail states were taken into consideration. It was determined that, by the effect of phosphorus doping the dominant conduction mechanism was the standard transport mechanism for all carbon contents.
Available online 30 December 2017
Effects of post-deposition annealing on sputtered SiO2/4H-SiC metal-oxide-semiconductor
Publication date: January 2018
Source:Solid-State Electronics, Volume 139 Author(s): Suhyeong Lee, Young Seok Kim, Hong Jeon Kang, Hyunwoo Kim, Min-Woo Ha, Hyeong Joon Kim Reactive sputtering followed by N2, NH3, O2, and NO post-deposition annealing (PDA) of SiO2 on 4H-SiC was investigated in this study. The results of ellipsometry, an etching test, and X-ray photoemission spectroscopy showed that N2 and NH3 PDA nitrified the SiO2. Devices using N2 and NH3 PDA exhibited a high gate leakage current and low breakdown field due to oxygen vacancies and incomplete oxynitride. SiO2/4H-SiC MOS capacitors were also fabricated and their electrical characteristics measured. The average breakdown fields of the devices using N2, NH3, O2, and NO PDA were 0.12, 0.17, 4.71 and 2.63
Available online 22 December 2017
Series resistance in different operation regime of junctionless transistors
Publication date: Available online 30 December 2017
Source:Solid-State Electronics Author(s): Dae-Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu-Tae Kim, G
Available online 21 December 2017
Insight into carrier lifetime impact on band-modulation devices
Publication date: Available online 22 December 2017
Source:Solid-State Electronics Author(s): Mukta Singh Parihar, Kyung Hwa Lee, Hyung Jin Park, Joris Lacord, S
Available online 21 December 2017
Application of CTLM Method Combining Interfacial Structure Characterization to Investigate Contact Formation of Silver Paste Metallization on Crystalline Silicon Solar Cells
Publication date: Available online 21 December 2017
Source:Solid-State Electronics Author(s): Shenghu Xiong, Xiao Yuan, Hua Tong, Yunxia Yang, Cui Liu, Xiaojun Ye, Yongsheng Li, Xianhao Wang, Lan Luo Circular transmission line model (CTLM) measurements were applied to study the contact formation mechanism of the silver paste metallization on n-type emitter of crystalline silicon solar cells. The electrical performance parameters
Available online 21 December 2017
Electrical characterization of vertically stacked p-FET SOI nanowires
Publication date: Available online 21 December 2017
Source:Solid-State Electronics Author(s): Bruna Cardoso Paz, Mika
Available online 21 December 2017
X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors
Publication date: Available online 21 December 2017
Source:Solid-State Electronics Author(s): Mingyo Park, Byung-Wook Min This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1
Available online 20 December 2017
Distributed parameter modeling to prevent charge cancellation for discrete thickness piezoelectric energy harvester
Publication date: Available online 21 December 2017
Source:Solid-State Electronics Author(s): M. Krishnasamy, Feng Qian, Lei Zuo, T.R. Lenka The charge cancellation due to the change of strain along single continuous piezoelectric layer can remarkably affect the performance of a cantilever based harvester. In this paper, analytical models using distributed parameters are developed with some extent of averting the charge cancellation in cantilever piezoelectric transducer where the piezoelectric layers are segmented at strain nodes of concerned vibration mode. The electrode of piezoelectric segments are parallelly connected with a single external resistive load in the 1st model (Model 1). While each bimorph piezoelectric layers are connected in parallel to a resistor to form an independent circuit in the 2nd model (Model 2). The analytical expressions of the closed-form electromechanical coupling responses in frequency domain under harmonic base excitation are derived based on the Euler–Bernoulli beam assumption for both models. The developed analytical models are validated by COMSOL and experimental results. The results demonstrate that the energy harvesting performance of the developed segmented piezoelectric layer models is better than the traditional model of continuous piezoelectric layer.
Available online 20 December 2017
Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field
Publication date: Available online 20 December 2017
Source:Solid-State Electronics Author(s): D. Damianos, G. Vitrant, M. Lei, J. Changala, A. Kaminski-Cachopo, D. Blanc-Pelissier, S. Cristoloveanu, I. Ionica In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.
Available online 20 December 2017
Enhanced transconductance in a double-gate graphene field-effect transistor
Publication date: Available online 20 December 2017
Source:Solid-State Electronics Author(s): Byeong-Woon Hwang, Hye-In Yeom, Daewon Kim, Choong-Ki Kim, Dongil Lee, Yang-Kyu Choi Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1
Available online 20 December 2017
Improve the performance of CZTSSe solar cells by applying a SnS BSF layer
Publication date: Available online 20 December 2017
Source:Solid-State Electronics Author(s): Mir Kazem Omrani, Mehran Minbashi, Nafiseh Memarian, Dae-Hwan Kim In this study, the CZTSSe (Cu2ZnSn(S,Se)4) solar cells, with Al/ZnO:Al/ZnO (i)/CdS/CZTSSe/Mo structure, have been simulated. The simulation results have been compared and validated with real experimental results. Next, suggestions for improving the performance of CZTSSe solar cell have been provided. A SnS layer has been used as back surface field (BSF) layer. Different physical parameters of SnS layer are investigated, and the optimum values are selected. It has been found that by inserting a BSF layer with optimum parameters, the efficiency of CZTSSe solar cell increases from 12.3% to 17.25% due to enhancement of both short-circuit current density (Jsc) and open circuit voltage (Voc). For this optimized cell structure, the maximum Jsc
Available online 20 December 2017
Thermal coupling and effect of subharmonic synchronization in a system of two VO2 based oscillators
Publication date: Available online 20 December 2017
Source:Solid-State Electronics Author(s): Andrey Velichko, Maksim Belyaev, Vadim Putrolaynen, Valentin Perminov, Alexander Pergament We explore a prototype of an oscillatory neural network (ONN) based on vanadium dioxide switching devices. The model system under study represents two oscillators based on thermally coupled VO2 switches. Numerical simulation shows that the effective action radius R TC of coupling depends both on the total energy released during switching and on the average power. It is experimentally and numerically proved that the temperature change
Available online 8 December 2017
Solution Processed Thin Film Transistor from Liquid Phase Exfoliated MoS2 Flakes
Publication date: Available online 20 December 2017
Source:Solid-State Electronics Author(s): Xiaoling Zeng, Hippolyte Hirwa, Sonia Metel, Valeria Nicolosi, Veit Wagner Two dimensional layers of dichalcogenide materials have attracted a lot of interests due to their potential applications in optoelectronics and energy storage. Hence, there is a large interest in establishing cheap, scalable processes for the production of low dimensional semiconducting dichalcogenide based films. In this work, well exfoliated MoS2 dispersions were prepared through a two-step liquid phase exfoliation process with N-methyl-pyrrolidone (NMP) and Isopropanol (IPA). The quality of the obtained MoS2 flakes was characterized by transmission electron microscopy, scanning electron microscopy, UV-Vis spectroscopy and Raman spectroscopy. For charge transport analysis, bottom-gate thin film transistors (TFTs) based on exfoliated MoS2 films were fabricated via spray coating technique. Electrical characterization of the obtained TFTs showed that adding a PMMA layer on top of the semiconductor lead to considerable improvements in the electrical performance. The analysis of the electrical characteristics suggests that the additional PMMA layer improves the charge transfer between adjacent flakes. Electrical measurements on TFTs with different channel length were used to separate the impact of the contact resistance and the channel resistance on the charge transport. The TFTs output curves showed non-linear current-voltage (I-V) characteristic. The non-linear behavior was attributed to the formation of Schottky barriers at the inter-flakes connection. In this work, we show a low-cost and scalable solution-based fabrication process that could boost the application of dichalcogenides in modern nanoelectronic devices.
Available online 6 December 2017
Kink effect in ultrathin FDSOI MOSFETs
Publication date: Available online 8 December 2017
Source:Solid-State Electronics Author(s): H.J. Park, M. Bawedin, H.G. Choi, S. Cristoloveanu Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10
Available online 2 December 2017
Static and low frequency noise characterization of ultra-thin body InAs MOSFETs
Publication date: Available online 6 December 2017
Source:Solid-State Electronics Author(s): T.A. Karatsori, M. Pastorek, C.G. Theodorou, A. Fadjie, N. Wichmann, L. Desplanque, X. Wallart, S. Bollaert, C.A. Dimitriadis, G. Ghibaudo A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.
Available online 2 December 2017
A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters
Publication date: Available online 2 December 2017
Source:Solid-State Electronics Author(s): S. Cristoloveanu, K.H. Lee, M.S. Parihar, H. El Dirani, J. Lacord, S. Martinie, C. Le Royer, J.-Ch. Barbe, X. Mescot, P. Fonteneau, Ph. Galy, F. Gamiz, C. Navarro, B. Cheng, M. Duan, F. Adamu-Lema, A. Asenov, Y. Taur, Y. Xu, Y-T. Kim, J. Wan, M. Bawedin The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10
December 2017
Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion
Publication date: Available online 2 December 2017
Source:Solid-State Electronics Author(s): T. Cazimajou, M. Legallais, M. Mouis, C. Ternon, B. Salem, G. Ghibaudo We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires.
December 2017
Editorial Board
Publication date: December 2017
Source:Solid-State Electronics, Volume 138

December 2017
Selected papers from the 7th IEEE International Nanoelectronics Conference (INEC 2016) and the 5th International Symposium on Next-Generation Electronics (ISNE 2016)
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Chi-Wah Kok, Wing-Shan Tam
December 2017
Review on peculiar issues of field emission in vacuum nanoelectronic devices
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Valeriu Filip, Lucian Drago
December 2017
Permittivity and temperature effects on rectification performance of self-switching diodes with different geometrical structures using two-dimensional device simulator
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): N.F. Zakaria, S.R. Kasjoo, Z. Zailan, M.M. Isa, S. Taking, M.K.M. Arshad Characterization on an InGaAs-based self-switching diode (SSD) using technology computer aided design (TCAD) aimed for optimizing the electrical rectification performance of the device is reported. The rectifying performance is mainly contributed by a parameter known as the curvature coefficient which is derived from the current-voltage (I-V) behavior of the device. As such, the curvature coefficient of SSD was analyzed in this work, not only by varying the device’s geometrical structure, but also by implementing different dielectric relative permittivity of the device’s trenches, ranging from 1.0 to 10. Furthermore, the simulations were performed under temperature range of 300–600K. The results showed that increased temperature degraded the SSD’s rectifying performance due to increased reverse current which can deteriorate the nonlinearity of the device’s I-V characteristic. Moreover, an improved curvature coefficient can be achieved using silicon dioxide (
December 2017
Analytical modeling on the drain current characteristics of gate-all-around TFET with the incorporation of short-channel effects
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Wanjie Xu, Hei Wong, Hiroshi Iwai, Jun Liu, Pei Qin An analytical model for describing the drain current characteristics of gate-all-around (GAA) tunneling field-effect transistor (TFET) is developed. Starting from potential distribution derived from Poisson’s equation in different regions along the channel, drain current model is developed based on Kane’s approach. The new model shows a better accuracy than the previously reported models. It is valid for larger ranges of bias conditions and channel length also. In particular, we have taken the effect of drain bias on the source junction tunneling into account. This effect is quite significant for the subthreshold conduction of short-channel devices. The validity of this model has been confirmed with TCAD simulation.
December 2017
Design and fabrication of low power GaAs/AlAs resonant tunneling diodes
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Mohamad Adzhar Md Zawawi, Mohamed Missous A very low peak voltage GaAs/AlAs resonant tunneling diode (RTD) grown by molecular beam epitaxy (MBE) has been studied in detail. Excellent growth control with atomic-layer precision resulted in a peak voltage of merely 0.28V (0.53V) in forward (reverse) direction. The peak current density in forward bias is around 15.4kA/cm2 with variation of within 7%. As for reverse bias, the peak current density is around 22.8kA/cm2 with 4% variation which implies excellent scalability. In this work, we have successfully demonstrated the fabrication of a GaAs/AlAs RTD by using a conventional optical lithography and chemical wet-etching with very low peak voltage suitable for application in low dc input power RTD-based sub-millimetre wave oscillators.
December 2017
Geometry and temperature effects on the threshold voltage characteristics of silicon nanowire MOS transistors
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Hei Wong, Qanqun Yu, Shurong Dong, Kuniyuki Kakushima, Hiroshi Iwai This work reports the observations of different geometry and temperature dependencies of electrical characteristics of silicon nanowire transistors with gate length of a couple microns. Several abnormal characteristics degradations were observed. As the gate lengths as well as the source/drain doping level of the devices under investigation were well beyond the punchthrough conditions, these observed characteristic degradations should not be due to conventional short-channel effects. We ascribed these observations to the charge transport along the corners/boundaries of the nanowires. Current enhancements were observed because of the higher mobility and larger density of states at the corners where the surface states have opposite effects on these parameters. Temperature dependence of the threshold voltage shows a linear decrease as the temperature increases. This trend is ascribed to the charge states at oxide/nanowire interfaces. Corners and surfaces of nanowire thus should play an important role for ultra-short nanowire transistors and that calls for shape of nanowire optimization for device design.
December 2017
Charge transfer effect for the La0.7Ca0.3MnO3/NiO heterostructure and novel interfacial ferromagnetism
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Xingkun Ning, Mingjing Chen, Shufang Wang, Guangsheng Fu We report the formation of new ferromagnetic (FM) states in antiferromagnetic (AFM) NiO at the interface with FM La0.7Ca0.3MnO3 (LCMO). The LCMO/NiO heterostructures exhibit an exchange bias field of 209Oe that vanishes as the temperature rises above 90K. A new magnetization temperature at 90K is observed and can be ascribed to Ni3+-O-Mn3+ superexchange interactions. Mn 3s and Ni 3p core-level spectra, measured by X-ray photoelectron spectroscopy, show a direct evidence of charge transfer effects of the type Mn4+-Ni2+
December 2017
Coupled and decoupled on-chip solenoid inductors with nanogranular magnetic cores
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Yuhan He, Luo Wang, Yicheng Wang, Huaiwu Zhang, Dongliang Peng, Feiming Bai On-chip integrated solenoid inductors with multilayered nanogranular magnetic cores have been designed and fabricated on silicon wafers. Both decoupled and coupled inductors with multilayered magnetic cores were studied. For the decoupled inductor, an inductance of 14.2nH or an equivalent inductance area density greater than 100nH/mm2 was obtained, which is about 14 times of that of the air-core inductor, and the quality factor is 7.5 at 130MHz. For the coupled inductor, an even higher peak quality factor of 17 was achieved at 300MHz, however, the inductance area density decreased to 34nH/mm2. The reason of the enhanced peak quality factor was attributed to less spike domains on the edge of the closure-loop shaped magnetic core, and therefore higher permeability and more uniform uniaxial anisotropy.
December 2017
Enhanced tunability of electrical and magnetic properties in (La,Sr)MnO3 thin films via field-assisted oxygen vacancy modulation
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Hon Fai Wong, Sheung Mei Ng, Wang Fai Cheng, Yukuai Liu, Xinxin Chen, Danny von Nordheim, Chee Leung Mak, Jiyan Dai, Bernd Ploss, Chi Wah Leung We investigated the tunability of the transport and magnetic properties in 7.5nm La0.7Sr0.3MnO3 (LSMO) epitaxial films in a field effect geometry with the ferroelectric copolymer P(VDF-TrFE) as the gate insulator. Two different switching behaviors were observed upon application of gate voltages with either high or low magnitudes. The application of single voltage pulses of alternating polarity with an amplitude high enough to switch the remanent polarization of the ferroelectric copolymer led to a 15% change of the resistance of the LSMO channel at temperature 300K (but less than 1% change at 20K). A minimal shift of the peak in the resistance-temperature plot was observed, implying that the Curie temperature TC of the manganite layer is not changed. Alternatively, the application of a chain of low voltage pulses was found to shift TC by more than 16K, and a change of the channel resistance by a 45% was obtained. We attribute this effect to the field-assisted injection and removal of oxygen vacancies in the LSMO layer, which can occur across the thickness of the oxide film. By controlling the oxygen migration, the low-field switching route offers a simple method for modulating the electric and magnetic properties of manganite films.
December 2017
Effect of post-annealing on sputtered MoS2 films
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): W.C. Wong, S.M. Ng, H.F. Wong, W.F. Cheng, C.L. Mak, C.W. Leung Typical routes for fabricating MoS2-based electronic devices rely on the transfer of as-prepared flakes to target substrates, which is incompatible with conventional device fabrication methods. In this work we investigated the preparation of MoS2 films by magnetron sputtering. By subjecting room-temperature sputtered MoS2 films to post-annealing at mild conditions (450°C in a nitrogen flow), crystalline MoS2 films were formed. To demonstrate the compatibility of the technique with typical device fabrication processes, MoS2 was prepared on epitaxial magnetic oxide films of La0.7Sr0.3MnO3, and the magnetic behavior of the films were unaffected by the post-annealing process. This work demonstrates the possibility of fabricating electronic and spintronic devices based on continuous MoS2 films prepared by sputtering deposition.
December 2017
Micro-patterning of resin-bonded NdFeB magnet for a fully integrated electromagnetic actuator
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Kai Tao, Jin Wu, Ajay Giri Prakash Kottapalli, Di Chen, Zhuoqing Yang, Guifu Ding, Sun Woh Lye, Jianmin Miao This paper reports a fully-integrated, batch-fabricated electromagnetic actuator which features micro-patterned NdFeB magnets. The entire actuator is fabricated through MEMS-compatible laminated surface micromachining technology, eliminating the requirement for further component assembly processes. The fabrication strategy allowed the entire volume of the actuator to be reduced to a small size of 2.5
December 2017
Ni antidot structure via single-step anodization of Al/Ni films
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Sheung Mei Ng, Wang Cheung Wong, Xu Fang, Hui Ye, Chi Wah Leung Antidot nanostructures were fabricated on Ni films by a single-step anodization process of magnetron-sputtered Al/Ni/W trilayers. Coercivity and saturation magnetization of the Ni layer were tuned by controlling the anodization time. Transmission electron microscopy was used to investigate the mechanism of the antidot formation process. The present study provides a simple and direct route for the fabrication of magnetic antidot nanostructures for device applications.
December 2017
Surface-dependent conductivity, transition type, and energy band structure in amorphous indium tin oxide films
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Yaqin Wang, Wu Tang Amorphous indium tin oxide (ITO) thin films were deposited on polymethylmethacrylate and polyethyleneterephthalate substrates by radio frequency magnetron sputtering at room temperature. An interesting substrate morphology effect of ITO films on the conductivity, optical transition type and energy band structure was observed. A simplified film system model with a square potential for surface morphology was employed to explain the difference of conductivity. The energy band structures were also calculated based on the theory of amorphous semiconductor. The conclusion demonstrated the width of optical band gap, as well as the relative position of the Fermi level and mobility edge, which can easily be extended to the band structure determination of other transparent conductive films.
December 2017
Improving the light output power of DUV-LED by introducing an intrinsic last quantum barrier interlayer on the high-quality AlN template
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Chia-Lung Tsai, Hsueh-Hsing Liu, Jun-Wei Chen, Chien-Pin Lu, Kazutada Ikenaga, Toshiya Tabuchi, Koh Matsumoto, Yi-Keng Fu We demonstrate that the light output power of deep ultraviolet light-emitting diodes (DUV-LEDs) can be improved by introducing an intrinsic last quantum barrier interlayer to a high quality AlN template. The light output power of the DUV-LEDs can be doubled by substituting the last quantum barrier with an intrinsic last quantum barrier (u-LQB)/Mg-doped LQB for only pure u-LQB in the same thickness with a 35A/cm2 injection current. It is believed that the improved performance of the DUV LED could be attributed to the decreased diffusion of Mg tunneling into MQW and the reduction of sub-band parasitic emissions.

The opto-thermal effect on encapsulated cholesteric liquid crystals
Publication date: December 2017
Source:Solid-State Electronics, Volume 138 Author(s): Yu-Sung Liu, Hui-Chi Lin, Kin-Min Yang In this study, we implemented a micro-encapsulated CLC electronic paper that is optically addressed and electrically erasable. The mechanism that forms spot diameters on the CLC films is discussed and verified through various experimental parameters, including the thickness of CLCs and Poly(2,3-dihydrothieno-1,4-dioxin)-poly(styrenesulfonate) (PEDOT:PSS), pump intensity, and pumping time. The opto-thermal effect, brought on by the PEDOT:PSS absorbing layer, causes the spot diameters on the cholesteric liquid crystal thin films to vary. According to our results, the spot diameter is larger for a sample with a thinner cholesteric liquid crystal layer with the same excitation conditions and same thickness of the PEDOT layer. The spot diameter is also larger for a sample with a thicker PEDOT under the same excitation conditions and same thickness of the cholesteric liquid crystal layer. We proposed a simple heat-conducting model to explain the experimental results, which qualitatively agree with this theoretical model.
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